NVIDIA Nemotron 3 Ultra Leads Open Models on Accuracy and Efficiency in Agentic RTL Coding

NVIDIA Model Sets New Bar for AI in Chip Design

NVIDIA has detailed the performance of its Nemotron 3 Ultra model, which, when integrated into an agentic workflow, achieves state-of-the-art results in Register Transfer Level (RTL) coding. Paired with the ACE-RTL agent, the model establishes a new standard for both accuracy and token efficiency, directly addressing a critical engineering bottleneck in the semiconductor industry. This development is significant as it provides a more practical path for automating complex hardware engineering tasks that have traditionally been limited by specialized human expertise and lengthy, iterative design cycles.

The system's performance was evaluated on the comprehensive Verilog design problems (CVDP) benchmark, where ACE-RTL with Nemotron 3 Ultra secured a 97.1% average pass rate across nine distinct task categories, outperforming models like GLM 5.2 and Kimi K2.6. A key differentiator is its operational efficiency; the model used up to 71% fewer tokens per iteration than Kimi K2.6. This reduction in computational cost is vital for the agent's iterative 'generate-test-reflect' process, which mimics how human engineers debug and refine hardware designs.

• Model Architecture: Hybrid Mamba-Attention Mixture-of-Experts (MoE)
• Active Parameters: 55B (out of 550B total)
• Context Length: 1M tokens
• Key Enabler: Training on a specialized synthetic RTL dataset focused on generation, editing, and debugging tasks.

The combined efficiency and accuracy of this system are lowering the barrier to integrating AI into production electronic design automation (EDA) workflows. Major EDA vendors are already announcing integrations, with Cadence incorporating it into its ChipStack AI SuperAgent, Siemens using it with its Questa One Agentic Toolkit, and Synopsys leveraging it in its AgentEngineer platform. This broad industry adoption signals a clear trend toward AI agents becoming standard tools for managing the increasing complexity and time-to-market pressures that define the modern semiconductor market.

The key takeaway is not just the model's performance but its economic viability for agentic systems. By achieving higher accuracy with drastically fewer tokens, NVIDIA demonstrates that a primary obstacle to deploying AI agents in complex, iterative domains like chip design—prohibitive inference cost and latency—is a solvable engineering problem. This makes the concept of autonomous, self-verifying EDA agents less of a research project and more of a near-term commercial reality.